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? semiconductor components industries, llc, 2012 october, 2012 ? rev. p0 1 publication order number: NCP81045/d NCP81045 product preview single synchronous step-down controller the NCP81045 is a synchronous stepdown controller for high performance systems battery ? power systems. the NCP81045 includes a high efficiency pwm controller . a pin is provided to allow two devices in interleaved operation. an internal power good voltage monitor tracks the smps output. NCP81045 also features soft ? start sequence, uvlo for v cc and switcher, overvoltage protection, overcurrent protection, undervoltage protection and thermal shutdown. the ic is packaged in qfn16. features ? 0.8% accuracy 0.8 v reference ? 4.5 v to 27 v battery/adaptor voltage range ? adjustable output voltage range: 0.8 v to 3.3 v ? synchronization interleaving between two NCP81045s ? skip mode for power saving operation at light load ? lossless inductor current sensing ? programmable transient ? response ? enhancement (tre) control ? programmable adaptive voltage positioning (avp) ? input supply feedforward control ? internal soft ? start ? integrated output discharge (soft ? stop) ? build ? in adaptive gate drivers ? pgood indication ? overvoltage, undervoltage and overcurrent protections ? thermal shutdown ? qfn16 package ? these devices are pb ? free and are rohs compliant typical applications ? notebook application ? system power this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. qfn16 case 485ap marking diagram http://onsemi.com 16 NCP81045 alyw 1 NCP81045 device code a = assembly location l = wafer lot y = year w = work week = pb ? free package 16 15 14 13 12 11 10 9 1 2 3 4 5678 vin vcc syn en vccp dl/treset pgnd cs+ pgood swm dh bst comp fb idrp/ocp cs ? /vo qfn16 (top view) NCP81045 (note: microdot may be in either location) 1 ordering information device package shipping ? ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. NCP81045mntxg qfn16 (pb ? free) 3000 / tape & reel
NCP81045 http://onsemi.com 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vin vcc syn en comp fb idrp/ocp cs ? /vo cs+ pgnd dl/treset vccp bst dh swn pgood pgh ? + ? + ? + ? + pgl uvp ovp control logic, protection, ramp generator and pwm logic NCP81045 over current detector avp control idrp/ocp detection uvlo control osc thermal shutdown uvlo control pgood level control enable master slave + ? disch cdiff current sense amplifier vcc vref vref+10% vref ? 10% vref ? 20% vref+15% 17 agnd tpad error amplifier low side driver high side driver + ? oc & tre detection figure 1. detail block diagram
NCP81045 http://onsemi.com 3 vout gnd vin pgood en_skip 16 9 1 2 3 4 5 12 10 11 8 7 6 15 14 13 vin vcc syn fb cs ? /vo cs+ pgnd dl/treset vccp bst dh swn pgood agnd comp idrp/ocp NCP81045 en_skip 5v figure 2. typical application circuit (single device operation)
NCP81045 http://onsemi.com 4 vout1 gnd1 vin en=ven_master 16 9 1 2 3 4 5 12 10 11 8 7 6 15 14 13 vin vcc syn fb cs ? /vo cs+ pgnd dl/treset vccp bst dh swn pgood agnd comp idrp/ocp NCP81045 en 5v vout2 gnd2 pgood2 16 9 1 2 3 4 5 12 10 11 8 7 6 15 14 13 vin vcc syn fb cs ? /vo cs+ pgnd dl/treset vccp bst dh swn pgood agnd comp idrp/ocp NCP81045 en pgood1 en=ven_slave slave master figure 3. typical application circuit (dual device operation)
NCP81045 http://onsemi.com 5 pin function description pin no. symbol description 1 vin input voltage used for feed forward in switcher operation. 2 vcc supply for analog circuit 3 syn synchronization interleaving use. 4 en this pin serves as two functions. enable: logic con trol for enabling the switcher. master/slave: to program the device as master or slave mode at dual device operation. 5 comp output of the error amplifier. 6 fb output voltage feed back. 7 idrp/ocp current limit programmable and setting for avp. 8 cs ? /vo inductor current differential sense inverting input. 9 cs+ inductor current differential sense non ? inverting input. 10 pgnd ground reference and high ? current return path for the bottom gate driver. 11 dl/treset gate driver output of bottom n ? channel mosfet. it also has the function for tre threshold setting. 12 vccp supply for bottom gate driver. 13 bst top gate driver input supply, a bootstrap capacitor connection between swn and this pin. 14 dh gate driver output of top n ? channel mosfet. 15 swn switch node between top mosfet and bottom mosfet. 16 pgood power good indicator of the output voltage. high impendence if power good (in regulation). low im- pendence if power not good. 17 tpad copper pad on bottom of ic used for heat sinking. this pin should be connected to the analog ground plane under the ic. absolute maximum ratings rating symbol value unit vcc power supply voltage to agnd v cc ? 0.3, 6.0 v vin supply to agnd v in ? 0.3, 30 v high ? side gate drive supply: bst to swn high ? side gate drive voltage: dh to swn low ? side gate drive supply: vccp to pgnd low ? side gate drive voltage: dl to pgnd v bst ? v swn, v dh ? v swn, v ccp ? v pgnd, v dl ? v pgnd, ? 0.3, 6.0 v input / output pins to agnd v io ? 0.3, 6.0 v switch node swn ? pgnd v swn ? 5 v (< 100 ns) 30 v v high ? side gate drive/low ? side gate drive outputs dh, dl ? 3(dc) v pgnd v pgnd ? 0.3, 0.3 v thermal characteristics thermal resistance junction ? to ? ambient (qfn16 package) r ja 48 c/w operating junction temperature range (note 1) t j ? 40 to + 150 c operating ambient temperature range t a ? 40 to + 85 c storage temperature range t stg ? 55 to +150 c moisture sensitivity level msl 1 ? stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. note: this device is esd sensitive. use standard esd precautions when handling. 1. internally limited by thermal shutdown, 150 c min.
NCP81045 http://onsemi.com 6 electrical characteristics (v in = 12 v, v cc = v ccp = 5 v, t a = ? 40 c to 85 c, unless other noted) characteristics symbol test conditions min typ max unit supply voltage input voltage v in 4.5 ? 27 v v cc operating voltage v cc 4.5 5.0 5.5 v supply current v cc quiescent supply current in master operation ivcc_master en = ven_master, v fb forced above regulation point. dh, dl are open 1.5 2.5 ma v cc quiescent supply current in slave operation ivcc_slave en = ven_slave, v fb forced above regulation point, dh, dl are open 1.5 2.5 ma v cc shutdown current ivcc_sd en = ven_disable, v cc = 5 v, true shutdown 1 a bst quiescent supply current in master operation ibst_master en = ven_master, v fb forced above regulation point, dh and dl are open, no boost trap diode 0.3 ma bst quiescent supply current in slave operation ibst_slave en = ven_slave, v fb forced above regulation point, dh and dl are open no boost trap diode 0.3 ma bst shutdown current ibst_sd en = 0 v 1 a vccp shutdown current ivccp_sd en = 0 v, v ccp = 5 v 1 a vin supply current ivin en = 5v, v in = 27 v 35 a vin shutdown current ivin_sd en = 0 v, v in = 27 v 1 a voltage ? monitor rising vcc threshold vccth+ wake up 4.05 4.25 4.48 v vcc uvlo hysteresis vcchys 200 275 400 mv rising vin threshold vinth+ wake up, design spec. (note 2) 3.4 3.8 4.2 v vin uvlo hysteresis vinhys (note 2) 200 500 800 mv power good high threshold vpgh pgood in from higher vo (pgood goes high) 120 125 130 % power good high hysteresis vpgh_hys pgood high hysteresis (pgood goes low) 5 % power good low threshold vpgl pgood in from lower vo (pgood goes high) 80 85 90 % power good low hysteresis vpgl_hys pgood low hysteresis (pgood goes low) ? 5 % power good high delay td_pgh after tss, (note 2) 1.25 ms power good low delay td_pgl (note 2) 1.5 s output overvoltage rising threshold ovpth+ with respect to error comparator threshold of 0.8 v 125 130 135 % overvoltage fault propagation delay ovptblk fb forced 2% above trip threshold (note 2) 1.5 s output undervoltage trip threshold uvpth with respect to error comparator threshold of 0.8 v 75 80 85 % output undervoltage protection blanking time uvptblk (note 2) ? 8/fsw ? s reference output internal reference voltage v ref 0.7936 0.8 0.8064 v 2. guaranteed by design, not tested in production.
NCP81045 http://onsemi.com 7 electrical characteristics (v in = 12 v, v cc = v ccp = 5 v, t a = ? 40 c to 85 c, unless other noted) characteristics unit max typ min test conditions symbol oscillator operation frequency f sw 270 300 330 khz overcurrent threshold total detection time t detect period of fb shorts to ground before ss 1.26 1.92 2.21 ms ocset detection time t_ocdet (note 2) 1.09 1.47 ms internal soft ? start soft ? start time tss 0.9 1.1 1.3 ms voltage error amplifier dc gain gain_vea (note 2) 88 db unity gain bandwidth bw_vea (note 2) 15 mhz slew rate sr_vea comp pin to gnd = 100 pf (note 2) 2.5 v/ s fb bias current ibias_fb 0.1 a output voltage swing vmax_ea isource_ea = 2 ma 3.3 3.5 v vmin_ea isink_ea = 2 ma 0.15 0.3 v differential current sense amplifier cs+ and cs ? common ? mode input signal range vcscom_max refer to agnd 3.5 v input bias current cs_iib ? 100 100 na input signal range cs_range ? 70 70 mv offset current at idrp idrp_offset (cs+) ? (cs ? ) = 0 v ? 1.0 1.0 a [(cs+) ? (cs ? )] to idrp gain idrp_gain (idrp/((cs+) ? (cs ? ))) (cs+) ? (cs ? ) = 10 mv, v(idrp) = 0.8 v 0.475 0.525 0.575 a/mv 0.425 0.625 a/mv current ? sense bandwidth bw_cs at ? 3db to dc gain (note 2) 20 mhz maximum idrp output voltage idrp_max (cs+) ? (cs ? ) = 70 mv, isource drops to 95% of the value when v (idrp) = 0.8 v 2.5 v minimum idrp output voltage idrp_min 0 v idrp output current i_idrp ? 1.0 35 a overcurrent protection setting overcurrent threshold (octh) detection current i_ocset sourced from ocp before soft ? start, rocset = 16.7 k is connected from ocp to agnd or fb 21.6 24 26.4 a ratio of oc threshold over ocset votlage k_ocset v((cs+) ? (cs ? )) / v_ocset (note 2) 0.1 ? ocset voltage for default fixed oc threshold vocset_dft rocset 2 k is connected from ocp to agnd or fb 100 mv ocset voltage for adjustable oc threshold vocset_adj rocset = 8.3 ~ 25 k is connected from ocp to agnd or fb 200 600 mv ocset voltage for oc disable vocset_dis rocset 35 k is connected from ocp to agnd or fb 720 mv default fixed oc threshold v_octh_dft (cs+) ? (cs ? ), pin ocp is shorted to agnd or fb 35 40 45 mv 2. guaranteed by design, not tested in production.
NCP81045 http://onsemi.com 8 electrical characteristics (v in = 12 v, v cc = v ccp = 5 v, t a = ? 40 c to 85 c, unless other noted) characteristics unit max typ min test conditions symbol overcurrent protection setting adjustable oc threshold v_octh ((cs+) ? (cs ? )) (cs+) ? (cs ? ), during oc threshold, set a voltage at pin ocp 15 20 25 mv 52 60 68 gate drivers dh pull ? high resistance rh_dh 200 ma source current 1 dh pull ? low resistance rl_dh 200 ma sink current 1 dl pull ? high resistance rh_dl 200 ma source current 1 dl pull ? low resistance rl_dl 200 ma sink current 0.5 dh source current isource_dh (note 2) 2.5 a dh sink current isink_dh (note 2) 2.5 a dl source current isource_dl (note 2) 2.5 a dl sink current isink_dl (note 2) 5 a dead time td_lh dl ? off to dh ? on (note 2) 20 ns td_hl dh ? off to dl ? on (note 2) 20 ns negative current detection threshold ncd_th swn ? pgnd, at en = 5 v ? 1 mv swn source leakage iswn_sd en = 0 v, swn = 0 v 1 a internal resistor from dh to swn r_dh_swn (note 2) 100 k control section en logic input voltage for disable ven_disable set as disable 0.7 1.0 1.3 v hysteresis 150 200 250 mv en logic input voltage for master mode ven_master set as master mode 1.7 1.95 2.25 v en logic input voltage for slave mode ven_slave set as slave mode 2.4 2.65 2.9 v hysteresis 100 175 250 mv en source current ien_source ven = 0 v 0.1 a en sink current ien_sink ven = 5 v 0.1 a pgood pin on resistance pgood_r i_pgood = 5 ma 100 pgood pin off current pgood_lk 1 a sync control sync pin leakage isync_lk set as slave mode, sync = 5 v 1 ua sync frequency f_sync (note 2) 1.2 mhz pulse width pw_sync (note 2) 416 ns clock level low v_clkl (note 2) 0 v clock level high v_clkh (note 2) 5 v sync driving capability sync_cl set as master mode, load capacitor between sync and gnd (note 2) 20 pf sync source current isync sync shorts to ground 20 mapp output discharge mode output discharge on ? resistance rdischarge en = 0 v 20 35 threshold for discharge off vth_disoff 0.2 0.3 0.4 v 2. guaranteed by design, not tested in production.
NCP81045 http://onsemi.com 9 electrical characteristics (v in = 12 v, v cc = v ccp = 5 v, t a = ? 40 c to 85 c, unless other noted) characteristics unit max typ min test conditions symbol tre setting tre threshold detection current i_treset sourced from dl in the short period before soft ? start. (rtre = 47 k is connected from dl to gnd 7.2 8 8.8 a detection voltage for tre threshold selection vdl_tre_1 (default) internal tre_th is set to 300 mv 500 600 700 mv vdl_tre_2 internal tre_th is set to 500 mv 300 450 vdl_tre_3 tre is disabled 0 250 tre comparator offset tre_os (note 2) 10 mv propagation delay of tre comparator td_pwm (note 2) 20 ns thermal shutdown thermal shutdown ts d (note 2) 150 c thermal shutdown hysteresis tsdhys (note 2) 25 c 2. guaranteed by design, not tested in production.
NCP81045 http://onsemi.com 10 typical operating characteristics 0.77 0.78 0.79 0.80 0.81 0.82 0.83 ? 40 ? 15 10 35 60 85 v fb v ref voltage (v) ambient temperature ( c) figure 4. v ref voltage vs ambient temperature ? 100 ? 50 0 50 100 150 200 ? 40 ? 15 10 35 60 85 ambient temperature ( c) v cc pin shutdown current (na) figure 5. v cc shutdown current vs ambient temperature 285 290 295 300 305 310 315 ? 40 ? 15 10 35 60 85 f sw switching frequency (khz) ambient temperature ( c) figure 6. switching frequency vs ambient temperature 0.20 0.30 0.40 0.50 0.60 0.70 0.80 ? 40 ? 15 10 35 60 85 ambient temperature ( c) idrp_gain ( a/mv) figure 7. idrp gain vs ambient temperature ? 20 ? 10 0 10 20 30 40 ? 40 ? 15 10 35 60 85 bst pin shutdown current (na) figure 8. bst shutdown current vs ambient temperature ambient temperature ( c) 37 38 39 40 41 42 43 ? 40 ? 15 10 35 60 85 default fix oc threshold (mv) ambient temperature ( c) figure 9. default fix oc threshold vs ambient temperature
NCP81045 http://onsemi.com 11 typical operating characteristics top to bottom: en, swn, vo, pgood top to bottom: en, swn, vo, pgood figure 10. powerup sequence figure 11. powerdown sequence top to bottom: swn_slave, vo_slave, swn_master, sync_clk top to bottom: swn_slave, vo_slave, swn_master, sync_clk figure 12. from unsync to sync figure 13. from sync to unsync top to bottom: swn, vo, io figure 14. typical transient
NCP81045 http://onsemi.com 12 detailed operating description general the NCP81045 synchronous stepdown power controller contains a pwm controller for wide battery/adaptor voltage range applications the NCP81045 includes power good voltage monitor, soft ? start, overcurrent protection, undervoltage protection, overvoltage protection and thermal shutdown. the NCP81045 features power saving function which can increase the efficiency at light load. it is ideal for battery operated systems. the ic is packaged in qfn16. control logic the internal control logic is powered by v cc . the device is controlled by an en pin. the en pin serves two functions. when voltage of en is below ven_disable, it shuts down the device. when the voltage of en is at the level of ven_master, the device is operating as master mode. when voltage level of en is at ven_ slave, the device is operating as slave mode. it should be noted that no matter the device is operating either at master or slave mode, the device is operating in the manner of auto power saving condition such that it operates as skip mode automatically at light load. when en is above ven_disable, the internal v ref is activated and power ? on reset occurs which resets all the protection faults. once v ref reaches its regulation voltage, an internal signal will wake up the supply undervoltage monitor which will assert a ?good? condition. in addition, the NCP81045 continuously monitors v cc and v in levels with undervoltage lockout (uvlo) function. single device operation the device is operating as single device operation when the sync pin is pull to ground. under this configuration, the device will use the internal clock for normal pwm operation. dual device operation (master/salve mode) the device is operating as master/slave mode if two devices are tied up together. (detail configuration please see the application schematic) one device is served as master and another one is served as slave. once they already, they are synchronized to each other and they are operating as ?interleaved? mode such that the phase shift of their switching clocks is 180 . it has the benefit that the amount of ripple current at the v in will be lower and hence lesser bulk capacitors at v in to save the confined pcb space and material cost. figure 15 and figure 16 show the difference when the devices are operating independently (unsynchronized) and operating at interleaved mode (synchronized). it can be seen that at the unsynchronized condition, the system is obviously noisy because of high ripple voltage at v in (ripple voltage directly reflects the amount of ripple current at v in ). once the devices are operating at interleaving mode, the overall v in ripple current is significantly reduced. top to bottom: vin ac voltage, swn_slave, swn_master figure 15. two devices are unsynchronized top to bottom: vin ac voltage, swn_slave, swn_master figure 16. two devices are in interleaved operation transient response enhancement (tre) for the conventional pwm controller in ccm, the fastest response time is one switching cycle in the worst case. to further improve transient response in ccm, a transient response enhancement circuitry is implemented inside the NCP81045. in ccm operation, the controller is continuously monitoring the comp pin output voltage of the error amplifier to detect the load transient events. the functional block diagram of tre is shown below. + r + c internal tre_th comp tre figure 17. block diagram of tre circuit
NCP81045 http://onsemi.com 13 once the large transient occurs, the comp signal may be large enough to exceed the threshold and then tre ?flag? signal will be asserted in a short period which is typically around one normal switching cycle. in this short period, the controller will be running at high frequency and hence has faster response. after that the controller comes back to normal switching frequency operation. we can program the internal tre threshold (tre_th). for detail please see the electrical table of ?tre setting? section. basically, the recommend internal tre threshold value is around 1.5 times of peak ? to ? peak value of the comp signal at ccm operation. the higher the internal tre_th, the lower sensitivity to load transient. the tre function can be disable by setting the rtre which is connecting to dl/tre pin to less than 25 k . for system component saving, it is usually set as default value, that is, rtre is open ( 75 k ) and internal tre_th is 300 mv typical. top to bottom swn, vo, transient signal figure 18. transient response with tre disable top to bottom swn, vo, transient signal figure 19. transient response with tre enable adaptive voltage positioning (avp) for applications with fast transient currents, adaptive voltage positioning can reduce peak ? to ? peak output voltage deviations due to load transients. with the use of avp, the output voltage allows to have some controlled sag when load current is applied. upon removal of the load, the output voltage returns no higher than the original level, just allowing one output transient peak to be cancelled over a load step up and release cycle. the amount of avp is adjustable. the behaviors of the v o waveforms with or without avp are depicted at figure 20. vo with avp vo without avp figure 20. adaptive voltage positioning + ? + + g i vref i drp rt rb rocp rs2 rs1 cs l dcr fb idrp/ocp cs+ cs ? comp vo figure 21. configuration for avp function the figure 21 shows how to realize the avp function. a current path is connecting to the fb pin via rocp resistor. rocp is not actually for avp function, indeed, rocp is used for ocp threshold value programming. the idrp/ocp pin has dual functions: ocp programming and avp. at the idrp/ocp pin, conceptually there is a current source which is modulated by current sensing amplifier. the output voltage v o with avp is: v o v o 0 i o *r ll (eq. 1) where i o is the load current, no load output voltage v o 0 is set by the external divider that is: v o 0 1 rt rb *v ref (eq. 2)
NCP81045 http://onsemi.com 14 the load line impendence r ll is given by: r ll dcr * gain_cs * rt * rs2 rs1 rs2 (eq. 3) where dcr is inductor dc resistance. gain_cs is a gain from [(cs+) ? (cs ? )] to idrp gain (at electrical table, the symbol is idrp_gain), the typical value is 0.525 a/mv. the avp function can be easily disable by shorting the rocp resistor into ground. from the equation we can see that the value of ?top? resistor rt can affect the amount of r ll , so it is recommended to define the amount of r ll frist before defining the compensation component value. and if the user wants to fine tune the compensation network for optimizing the transient performance, it is not recommend to adjust the value of rt. otherwise, both transient performance and avp amount will be af fected. the following diagram shows the typical waveform of avp. note that the rt typical value should be above 1 k . top to bottom: swn, vo, transient signal figure 22. typical waveform of avp over current protection (ocp) the NCP81045 protects power system if over current event occurs. the current is continuously monitored by the differential current sensing circuit. the current limit threshold voltage vocset can be programmed by resistor rocset connecting at the idrp/ocp pin. however, fixed default vocset can be achieved if rocset is less than 2 k . if the inductor current exceeds the current threshold continuously, the top gate driver will be turned off cycle by cycle. if it happens over consecutive 16 clock cycles time (16 x 1/f sw ), the device is latched off such that top and bottom gate drivers are off. en resets or power recycle the device can exit the fault. the following diagram shows the typical behavior of ocp. top to bottom : swn, vo, pgood, io figure 23. overcurrent protection the NCP81045 uses lossless inductor current sensing for acquiring current information. in addition, the threshold ocp voltage can be programmed to some desired value by setting the programming resistor rocp. + ? + + g i vref i drp rt rb rocp rs2 rs1 cs l dcr fb idrp/ocp cs+ cs ? comp + ? + + g i vref i drp rt rb rocp rs2 rs1 cs l dcr fb idrp/ocp cs+ cs ? comp with avp without avp vo vo figure 24. ocp configuration it should be noted that there are two configurations for rocp resistor. if adaptor v oltage position (a vp) is used, the rocp should be connected to fb pin. if avp is not used, the rocp should be connected to ground. at the idrp/ocp pin, there is a constant current(24 a typ.) flowing out during the programming stage at system start up. this is used to sense
NCP81045 http://onsemi.com 15 the voltage level which is developed by a resistor rocp so as to program the overcurrent detection threshold voltage. for typical application, the v octh is set as default value(40 mv typ) by setting rocp = 0 , or directly short the idrp/ocp pin to ground. it has the benefit of saving one component at application board. for other programming values of v octh , please refer to the electrical table of ?overcurrent protection setting? section. guidelines for selecting ocp trip component 1. choose the value of rocp for v octh selection. 2. define the dc value of ocp trip point(i ocp_dc ) that you want. the typical value is 1.5 to 1.8 times of maximum loading current. for example, if maximum loading is 10 a, then set ocp trip point at 15 a to 18 a. 3. calculate the inductor peak current (i pk )which is estimated by the equation: i pk i ocp_dc v o *(v in v o ) 2*v in *f sw *l o (eq. 4) 4. check with inductor datasheet to find out the value of inductor dc resistance dcr, then calculate the rs1, rs2 dividing factor k based on the equation: k v octh i pk *dcr (eq. 5) 5. select c s value between 100 nf to 200 nf. typically, 100 nf will be used. 6. calculate rs1 value by the equation: rs1 l k * dcr * cs (eq. 6) 7. calculate rs2 value by the equation: rs2 k*rs1 1 k (eq. 7) 8. hence, all the current sense components rs1, rs2, cs had been found for taget i ocp_dc . 9. if rs2 is not used (open), set k = 1, at that moment, the i pk will be restricted by: i pk v octh dcr (eq. 8) overvoltage protection (ovp) when v fb voltage is above ovpth+ of the nominal v fb voltage for over 1.5 s blanking time, an ov fault is set. at that moment, the top gate drive is turned off and the bottom gate drive is turned on until the v fb below lower under voltage (uv) threshold and bottom gate drive is turned on again whenever v fb goes above upper uv threshold. en resets or power recycle the device can exit the fault. the following diagram shows the typical waveform when ovp event occurs. top to bottom : swn, dl, vo, pgood figure 25. overvoltage protection undervoltage protection (uvp) an uvp circuit monitors the v fb voltage to detect under voltage eve nt. the under vol tage limit is 80% (typical) of the nominal v fb voltage. if the v fb voltage is below this threshold over consecutive 8 clock cycles, an uv fault is set and the device is latched off such that both top and bottom gate drives are off. en resets or power recycle the device can exit the fault. top to bottom : swn, vo, pgood figure 26. undervoltage protection thermal shutdown the ic will shutdown if the die temperature exceeds 150 c. the ic restarts operation only after the junction temperature drops below 125 c.
NCP81045 http://onsemi.com 16 bst vccp dl/treset pgnd cs+ comp vcc syn en vin 4 3 2 1 5 16 12 9 10 11 13 14 15 6 7 8 fb idrp/ocp cs ? /vo dh swn pgood vin vout pgnd c28 d22 r29 r220 r22 c24 r28 m1 m3 r210 c29 r27 m2 m4 r26 c212 r212 d21 l1 r25 r24 c27 c26 c2 c216 j2 d23 1 2 3 1 ? 2 = ocp only 3 ? 2 = ocp + avp c1 c25 c213 comp c3 r7 m5 led1 pgood pgood +5v agnd sync r2 c21 c22 c23 r21 r216 jp2 jp3 r23 r224 c214 r213 r215 r211 c215 r214 r223 pgnd j21 swn dh dl pgnd pgnd fb en tpad pgnd agnd NCP81045 u1 r1 figure 27. demo board schematic
NCP81045 http://onsemi.com 17 package dimensions qfn16 4x4, 0.65p case 485ap issue a 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. ?? ?? ?? b a 0.15 c top view side view bottom view pin 1 reference 0.10 c 0.08 c (a3) c 16x 16x 0.10 c 0.05 c a b note 3 k 16x detail a dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.25 0.35 d 4.00 bsc d2 2.00 2.20 e 4.00 bsc e2 2.00 2.20 e 0.65 bsc k 0.20 ??? l 0.45 0.65 dimensions: millimeters *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. mounting footprint* 16x 16x pitch l1 ??? 0.15 l1 detail a l optional lead constructions ??? 4.30 2.25 2.25 4.30 1 0.65 0.78 0.35 outline pkg 2x 2x detail b note 4 on semiconductor and are registered trademar ks of semiconductor components industries, llc (s cillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to an y products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of th e application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products ar e not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associ ated with such unintended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action em ployer. this literature is subject to all applicable copyrig ht laws and is not fo r resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCP81045/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative

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